发明名称 VARIABLE LENGTH DECODING CIRCUIT
摘要 PURPOSE:To prevent the reduction in the coding efficiency by switching a variable length code and an equal length code and transmitting the result. CONSTITUTION:Data inputted to an input terminal 1 is outputted as it is when it is equal length code and after being converted into an equal length code by a variable length decoder 2 when the data is a variable length code an output terminal 9. A counter circuit 4 counts the quantity of information of the equal length code and a counter circuit 6 counts the quantity of information of the variable length code converted from the equal length code. Only when the count of the counter circuit 6 is larger than the count of the counter circuit 4, a selection circuit 3 selects the data at the input terminal 1 and selects the output of the variable length decoder 2 in other cases. Thus, the deterioration in the coding efficiency is prevented.
申请公布号 JPS6412621(A) 申请公布日期 1989.01.17
申请号 JP19870167684 申请日期 1987.07.07
申请人 NEC CORP 发明人 OKAJIMA MASAYUKI
分类号 H03M7/40;H03M7/48 主分类号 H03M7/40
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