| 摘要 |
<p>A digital BiCMOS memory chip (Fig. 2) includes a row of memory cells (40), and an address decoder (50) for the row of cells. Each of the memory cells is constructed of field-effect transistors (41, 42, 43, 44) which operate at CMOS voltage levels (-3.2v, -0.8v), whereas the address decoder (50) is constructed of bipolar transistors (51-1 thru 51-N, 52, 56) which operate at ECL voltage levels (-2.4x, -3.2x). A direct connection is made via a row line (Rx) from the addresss decoder (50) to the row of memory cells with no ECL-to-CMOS voltage level converter lying therebetween. This direct connection is made operable by properly selecting all voltages that occur on certain nodes (N2, N3) in the address decoder and the memory cell; and, that enables the memory to be read faster plus occupy less chip space plus dissipate less power than the prior art.</p> |
