Semiconductor storage cell for multi-port random access memory - occupies smaller area of CMOS integrated circuit substrate by virtue of elimination of gate isolation transistors

摘要

A data storage circuit (71) is formed of p-MOS transistors (1a,1b) and n-MOS transistors (2a,2b). Address gates are provided by p-MOS transistors (1c,1d) and n-MOS transistors (2c,2d). All four p-MOS transistors (1c,1a,1b,1d) are connected in that order series in the p-type defect regions of an elementary cell, and the four n-MOS transistors (2c,2a,2b,2d) likewise in n-type defect regions. No transistors are required for gate isolation. Separate bit lines (BLA bar, BLB) and a pair (BLC,BLC bar) are connected to readout amplifiers for three address ports. USE/ADVANTAGE - Esp. in gate array. Integration density is increased so that less chip area is occupied.