发明名称 POWER-ON RESET SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To generate a reset signal surely, by respectively setting the output point of each inverter at an odd number stage among inverters to the circuit power supply voltage, and that of an even number of stage to the reference potential. CONSTITUTION:Inverters 42-45 in cascade connection are provided between the output A of a time constant circuit 41 and a reset terminal -R of an external circuit 1. Capacitors C2 and C3 are respectively connected between outputs B, D of odd step inverters 42, 44 and the output line of a circuit power supply 2, and the output, B, D are pulled up to the power supply voltage for a given period after the application of power supply. Capacitors C4, C5 are respectively connected between outputs C, E of the even step inverters 43, 45 and ground being the reference voltage to pull down the outputs C, E to ground for a given period after the application of power supply.
申请公布号 JPS579131(A) 申请公布日期 1982.01.18
申请号 JP19800083152 申请日期 1980.06.19
申请人 PIONEER ELECTRONIC CORP 发明人 HIRASHIMA KUNIHIKO
分类号 H03K17/22 主分类号 H03K17/22
代理机构 代理人
主权项
地址
您可能感兴趣的专利