| 摘要 |
PURPOSE:To stably set the delay time of a control object by generating a reference clock signal by performing the prescribed delay and frequency division to an input clock signal, and generating a control signal which becomes significant from a prescribed variation point of the input clock signal, which the reference clock signal is significant. CONSTITUTION:The delaying circuit is provided with a delaying means 4 and a frequency dividing means 8 for generating a reference clock signal B by performing the prescribed delay and frequency division to an input clock signal A, and a control signal generating means 10 for generating a control signal C which becomes significant from a prescribed variation point of the input clock signal A, while the reference clock signal B is significant, and by this control signal C, a control object 3 is controlled. Accordingly, for instance, in the case a power supply voltage is high, the time until a signal Y is defined, based on the input clock signal A as a reference becomes short, and the time until a rise of the reference clock signal B from the input clock signal A also becomes short. In such a way, fluctuation width by which a delay time of the control object is shifted from a set value due to whether the power supply voltage, etc., are high or low can be made small. |
