| 摘要 |
PURPOSE:To control an integrated circuit by selecting an expected address accurately by activating a passive internal control signal while an address input signal is being inputted, and then by passivating it. CONSTITUTION:An address decoder 2 outputs a control signal (CS) 4. This CS signal 4 is inputted to a buffer circuit 5 and an inverter circuit 6 in an internal control signal generating circuit 13. The output signal of this buffer circuit 5 is inputted to a delay circuit 7, which outputs an output signal 8 delayed by a delay time D1. The output signal of the inverter circuit 6, on the other hand, is inputted to a dalay circuit 9, whose output signal 10 rises a dealy time D2 later. Therefore, an AND circuit 11 ANDs the output signal and output signal 10 to output an internal CS signal 12. |
