| 摘要 |
<p>A system for controlling communications among a computer processing unit and a plurality of peripheral devices (120,124,132) which are arrayed in operative connection with a plurality of external buses (118,122,128). The system comprises a bus control circuit (90) for effecting operative routing of address information regarding a respective peripheral device from the computer processing unit to an appropriate external bus, the respective peripheral device being in operative connection with the appropriate external bus. The bus control circuit also effects operative routing of data information from the respective peripheral device to another of the plurality of pheripheral devices or to the computer processing unit according to the address information. The system further comprises a plurality of buffers (21,29,37) for establishing operative interfaces between the system and each of the plurality of external buses and an internal bus for facilitating communications among the plurality of buffers, the bus control circuit, and the computer processing unit. The bus control circuit enables operative interconnections to the internal bus by the plurality of buffers and the computer processing unit and includes an information storage unit (91) for retaining stored routing information representing all operative interconnections which can operatively occur, the bus control circuit effecting such enabling according to the stored routing information. <IMAGE></p> |
