发明名称
摘要 PURPOSE:To confirm that an integrated circuit operates normally at least up to a detection level, by suppressing the output of a reset signal out of a source voltage detecting circuit by an external set signal arriving at a terminal of the integrated circuit. CONSTITUTION:When an L-level signal is supplied to the test mode signal terminal 9 provided to the integrated circuit 1, the integrated circuit 1 suppress the output of the source voltage detecting circuit (g) in test mode by AND logic 7. On the other hand, an H-level signal is supplied to the test mode signal terminal 9 in a normal operation state and a test state for resetting, so the output of the source voltage detecting circuit part 8 is supplied to an operation function part 2 through the AND logic 7. For this purpose, a source voltage VCC is set to, for example, 4.0V lower than 4.2V as the detection level VT in test mode, confirming whether the integrated circuit 1 operates normally or not.
申请公布号 JPH0411893(B2) 申请公布日期 1992.03.02
申请号 JP19820113308 申请日期 1982.06.30
申请人 FUJITSU LTD 发明人 FUJITA KOICHI;SHIRATO MORITOSHI
分类号 G06F11/22;G06F1/24;G06F11/00 主分类号 G06F11/22
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