发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To accelerate the transient response of frequency and to heighten stability in a stationary state by providing a control circuit at the rear stage of a phase frequency comparator, and controlling the width and the number of control pulses by the control circuit. CONSTITUTION:The signal of a voltage controlled oscillator 9, after being frequency-devided by a variable frequency divider 5, is inputted to the phase frequency comparator 4. At such a time, the number of frequency divisions of the variable frequency divider 5 is controlled by a signal inputted from the number of frequency divisions input terminal 2. The output of the variable frequency divider 5 is phase- and frequency-compared with the signal of a reference frequency oscillator 3 at the phase frequency comparator 4, then, the control pulse in accordance with the relative phase difference and frequency difference of them is generated. The control pulse outputted from the phase frequency comparator 4 is inputted to the control circuit 6, which controls the width and the number of control pulses.
申请公布号 JPH0463021(A) 申请公布日期 1992.02.28
申请号 JP19900173033 申请日期 1990.06.30
申请人 NEC CORP 发明人 NORIMATSU HIDEHIKO
分类号 H03L7/18;H03L7/08;H03L7/10 主分类号 H03L7/18
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