发明名称 PLL CIRCUIT FOR VIDEO SIGNAL
摘要 PURPOSE:To attain stable sampling clock supply by controlling an oscillating frequency of a voltage controlled oscillator when a phase difference of a phase of a horizontal synchronizing signal and a phase of a frequency division signal of the sampling clock is at the outside of a prescribed range. CONSTITUTION:As a means to control a voltage controlled oscillator 400, a control circuit (shown in alternate long and short dash line in figure) including a protection period generating circuit 700 and a phase difference conversion circuit 800 is provided. Then a protection range is provided with respect to a phase difference between a horizontal synchronizing signal of an input video signal and a frequency division signal of a sampling clock outputted from the voltage controlled oscillator 400 and only when a phase difference in excess of the protection range, the oscillating frequency of the voltage controlled oscillator is controlled. Thus, a small change in the horizontal synchronizing signal in the input video signal is absorbed and the sampling clock with a stable frequency synchronously with the horizontal synchronizing signal is generated from the voltage controlled oscillator 400.
申请公布号 JPH0461492(A) 申请公布日期 1992.02.27
申请号 JP19900169979 申请日期 1990.06.29
申请人 NEC CORP;NEC MIYAGI LTD 发明人 CHO FUJIO;ASHIDA KOJI
分类号 H04N5/7826;H03L7/06;H04N5/06;H04N5/66;H04N5/782;H04N7/24;H04N9/44;H04N9/45;H04N11/04;H04N19/00;H04N19/59;H04N19/85 主分类号 H04N5/7826
代理机构 代理人
主权项
地址