| 摘要 |
PURPOSE:To eliminate the need for a capture range more than a required range and to generate a clock signal with high stability by providing a reference oscillating frequency search function so that a reference signal frequency and an oscillated frequency of a VCO at an open loop state of a PLL section are almost the same. CONSTITUTION:A switch 6 is turned off while a control signal 17 from a timing control section 8 is logical H, a frequency control section 14 counts up a signal 18 with an optional frequency outputted from the control section 8 when a PLL is opened to control a frequency variable device 15. Thus, the oscillating frequency of a VCO 1 changes stepwise. When the output of the VCO 1 is higher than the output of a crystal oscillator 3, control signals 19a-19d from the control section 14 are latched at a frequency comparison section 13 and the frequency at that time is a free oscillating frequency. After the frequency search, a switch 16 is turned on to apply PLL control and a stable clock signal is generated in response to a reference clock signal over a wide range without a wide capture range taken. |
