发明名称 PARALLEL GENERATING CIRCUIT FOR SERIAL PN PATTERNS AND CONFIGURATION METHOD FOR SAID CIRCUIT
摘要 <p>PURPOSE:To output a serial PN pattern of an optional degree in parallel at an optional width by forming a degree (n) feedback shift register circuit with n-stages of shift registers and an EOR circuit exclusively ORing an output of the final stage register and an output of the m-th stage and applying the EOR to the 1st stage register. CONSTITUTION:An nXn-dimension square matrix expressing the relation between an n-dimension numerical vector comprising each input of n-set of registers in an n-stages of feedback shift registers and an n-dimension numerical vector comprising each output is obtained and a square matrix being the I-th power of the nXn-dimension square matrix is obtained, and each square matrix being the p-th power of the nXn-dimension square matrix is obtained by each value (p) satisfying equation of J>=p>=I+1. Moreover, a matrix of (n+J-1)-rows and n-columns whose 1st-n-th row element is that of the nXn-dimension square matrix is obtained. Then circuits each relating each input to each output of each of the n-sets of registers as to each (p) in a range of J>=p>=I+1 are formed and a selector is provided, which selects only a circuit corresponding to the designated value (p) and makes required connection.</p>
申请公布号 JPH0457407(A) 申请公布日期 1992.02.25
申请号 JP19900166878 申请日期 1990.06.27
申请人 FUJITSU LTD 发明人 KASAHARA HIROYUKI
分类号 H03K3/84;H04L7/00 主分类号 H03K3/84
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