| 摘要 |
PURPOSE:To enable efficient backup and to shorten time for it by continuously writing continuous data blocks while successively selecting plural writable/ erasable memories. CONSTITUTION:When address signals A6 and A7 are inputted through address control lines 21 and 22 from a CPU, an address decoder 15 decodes these signals and prepares a chip select signal 17 for designating one of EEPROM 11-14. Thus, the EEPROM 11 is selected and the data of 64 bytes are continuously written. Next, when the CPU sets the address signals A6 and A7 to L and H respectively, the address decoder 15 changes the signal 17 to L and holds the other signals at H. Thus, the EEPROM 12 is selected and the data are continuously written. Afterwards, the write operation is repeated similarly. |
