发明名称 FAULT PROCESSING SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To obtain alternate processing address for all the input/output control parts by providing flag registers in accordance with plural input/output control parts. CONSTITUTION:When a fault occurs in the address of the input/output control part, a bit in accordance with the flag register 4 is turned on, therefore, the output signal C of a selective circuit 5 is sent in '1'. The bit 0 of an address register 6 is sent to a signal line d0. The OR of the signal C and the signal d0 is found at an OR circuit 7, and the bit e0 of an address bus is sent in '1'. In other words, 16 data of the address of the input/output control part are converted to the 16 data, and the address 16 of the input/output control part can perform alternate processing.
申请公布号 JPH0457133(A) 申请公布日期 1992.02.24
申请号 JP19900166578 申请日期 1990.06.27
申请人 HITACHI LTD 发明人 WAKAO HIDEKI
分类号 G06F11/20;G06F11/22;G06F13/00 主分类号 G06F11/20
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