| 摘要 |
The check and detection period of the pulse train is reduced to a half with out decreasing the resolution by adding a simple delay unit. The circuit includes a flip-flop (3) for generating gate signal, a gate unit (4) for passing the pulse train during high level of the gate signal, a counter (5) for counting the pulses passed through the gate unit (4), a first delay (6) for generating pulse output signal having a duration, a latch (7) for latching the counted value by the pulse output signal, a second delay (8) for delaying the pulse output signal to generate signal for resetting the counter, and a third delay (10) for delaying the output signal of the second delay (8) to generate the signal for resetting a frequency divier (2).
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