发明名称 OVERDELAY TESTING SYSTEM BETWEEN SYNCHRONOUS FF'S
摘要 PURPOSE:To improve a testing efficiency by equalizing the output values of target FFs to the same value when an overdelay and a racing occur between a source FF to be tested and the target FF. CONSTITUTION:A test pattern 4 in which an input of a source FF 1 is inverted from a first clock to a second clock and the output of the source FF 1 is inverted by the fist clock, is used. If the output value of a target FF 2 after a second clock coincides with an expected value set by the pattern 4, i.e., the output value when the target F 2 is correctly operated, decisions in which no overdelay occurs between the source FF 1 and the target FF 2 and further no racing occurs are performed once, thereby enhancing the testing efficiency of the overdelay test.
申请公布号 JPH0455774(A) 申请公布日期 1992.02.24
申请号 JP19900167943 申请日期 1990.06.26
申请人 FUJITSU LTD 发明人 HIDAKA HISAO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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