发明名称 INTEGRATED CIRCUIT FOR PEAK DETECTION
摘要 PURPOSE:To make unnecessary complicated burst interleaving circuit, by changing a clamp voltage of a clamp circuit at a burst signal and video signal period and operating the differential amplifier at the post stage only at the burst signal period. CONSTITUTION:A burst gate pulse from an input terminal 2 is at 1, that is, at 1, that is, at the burst signal period, then a voltage E3 is obtained at the base of a transistor (TR)Q8. When a negative peak of a burst signal is lower than E3- Vbe (where; Vbe is a voltage between the base and the emitter of the TRQ8), the TRQ8 is conductive, a capacitor C2 is charged and the negative side of the burst signal is clamped to E3-Vbc. On the other hand, a TRQ12 is conductive only at the burst signal period with the burst gate pulse to flow the operating current of TRsQ9, Q10 cinstituting the differential amplifier. Thus, at this period, when the base voltage of the TRQ9 is higher than the base voltage of the TRQ10, a current flows to the collector of the TRQ9 to increase the DC voltage at an output terminal 3.
申请公布号 JPS5715593(A) 申请公布日期 1982.01.26
申请号 JP19800089226 申请日期 1980.07.02
申请人 HITACHI LTD 发明人 NAKAGAWA HIMIO;TOGAMI TAKATOSHI
分类号 H04N9/68;H04N9/64;H04N9/793 主分类号 H04N9/68
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