发明名称 TESTING METHOD OF INTEGRATED CIRCUIT CHIP
摘要 <p>PURPOSE: To provide simulated site test and actual site test for integrated circuit chip by providing a contact corresponding to the contact of semiconductor chip and defining the contact of carrier as a chip carrier having a dendrite surface. CONSTITUTION: A semiconductor circuit chip is placed on a board or a test jig while facing a connector on the board. The board or jig has the dendrite in structure including a conductive pad or substrate, smooth Pd lower layer and upper layer such as a pole-shaped Pd layer on the connecting plane, contact or pad of chip. Then, the chip and the board are contacted and compressing force is applied to the chip and the board. Afterwards, various logic tests and memory tests are performed to the integrated circuit chip while applying power between the input and the ground, and unsuccessful chip is discarded but the successful chip is bonded to the board between the bonding pad and the dendritic surface.</p>
申请公布号 JPH06252226(A) 申请公布日期 1994.09.09
申请号 JP19940013281 申请日期 1994.02.07
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 ANIRUKUMARU CHINUPURASADO BATSUTO;REO REIMONDO BUDA;ROBAATO DAGURASU EDOWAAZU;POORU JIYOOZEFU HAATO;ANSONII POORU INGURAHAMU;BUOYA RISUTA MARUKOBUICHI;JIYAINARU AABEDEIIN MOTSURA;RICHIYAADO JIERARUDO MAAFUII;JIYOOJI SAKUSENMAIYAA JIYUNIA;JIYOOJI FUREDERITSUKU UOOKAA;BETSUTO JIEI HOUEEREN;RICHIYAADO SUCHIYUAATO ZARU
分类号 G01R31/28;H01L21/60;H01L21/66;(IPC1-7):H01L21/66 主分类号 G01R31/28
代理机构 代理人
主权项
地址