发明名称 CLOCK DRIVER CIRCUIT
摘要 PURPOSE:To extend a period when both 1st and 2nd outputs are at a low level by energizing an N-channel MOSFET when the potential of a terminal goes from a high level to a low level so as to make the operation of a clock driver stable. CONSTITUTION:Complementary signals are inputted respectively to 1st and 2nd input terminals, when the potential at a point 5 changes from a high level to a low level, an N-channel MOSFET 9 is energized to change a at high speed and similarly the potential at a point 6 changes from a low level to a high level, then an N-channel MOSFET 10 is energized, which is changed fast. Thus, the potential at the points 5, 6 starts changing from a ground level without fail, and even when the time constant comprising RC is increased to extend a period when both 1st and 2nd outputs are at a low level, stable operation is implemented.
申请公布号 JPH0454721(A) 申请公布日期 1992.02.21
申请号 JP19900165916 申请日期 1990.06.25
申请人 NEC CORP 发明人 NARAHARA TETSUYA
分类号 H01L29/78;H03K3/037;H03K5/151 主分类号 H01L29/78
代理机构 代理人
主权项
地址