发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To arbitrarily set modes of holding of the present condition, forced turn-on, and forced turn-off with regard to any output by forcing each output of a second logic circuit to a set output in response to an abnormality direction output. CONSTITUTION:When a connector terminal 31-1 is turned on and becomes fault/drawing, an E point and an F point are varied from 'L' to 'H', and from 'H' to 'L', respectively. However, a connector terminal 32 is also turned off simultaneously, an A point becomes 'H' from 'L', and since a variation of the A point is quicker than an input of an OR circuit 38-1, that is, a variation of the E point, outputs of OR circuits 38-1, 39-1 become 'H', and these 'H's pass through AND circuit 42-1, 43-1, and OR circuit 44-1, and an AND circuit 45-1, and are inputted to -S and -R terminals of an FF46-1. That is, before the E point becomes 'H', both the -S and -R input terminals of the FF46, become 'H', and a Q output of 46-1, is not varied. That is, a variation of the E point does not appear in the Q output. In such a way, the present condition of the output is held.
申请公布号 JPH0454644(A) 申请公布日期 1992.02.21
申请号 JP19900166157 申请日期 1990.06.25
申请人 SHIMADZU CORP 发明人 NISHIGUCHI OSAMU
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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