| 摘要 |
The multiple-layer neural network receiving an input with m bits and generating an output with n bits includes a neuron linking, in cascade, a pair of CMOS inverters possessing an output node with inversion and an output node without inversion, an input layer (L0) of m neurons for m-bit input generation, an output layer (L3) of n neurons with n-bit output, at least one inaccessible layer (L1, L2) of n neurons for transfer from the input layer (L0) to the upper inaccessible layer or to the output layer (L3), an input synapsis group (S1) for linking the input layer (L0) to the output layer (L3) and to at least one inaccessible layer, at least one transfer synapsis group (S1, S2) so as to connect an inaccessible layer to the higher inaccessible layer or to the output layer (L3), and a polarisation synapsis group (S4) for each input node of neurons of the inaccessible layers (L1, L2) and of the output layer (L3). <IMAGE>
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