| 摘要 |
The invention relates to a very fast memory bit cell for implementation in VLSI technics. Many bit cells could be packed very dense. The bit cell includes: a cell circuit (T1, T2, L1, L2, D1, D2; T1, T2, I1, I2, D1, D2) in which a bit value is storable, said value being either 'true' or 'false'; a first connection (Vcc) which is constantly provided with a supply voltage, a second, a third and a fourth connection (acc, d, d*) each of which is settable in different control states; said cell circuit being such that each combination of said control states on said second, third and fourth connection is setting said memory bit cell in an individual among a set of functional states. |
