Buffer memory for equalising phase variations - has control for multiplexer, intermediate memory, and input data memory

摘要

The variations take place between an input clock pulse signal, derived from input data, and a local clock pulse signal of a reception circuit with a memory (2) for input data with an address from a write generator (7). A control (10) acts on a multiplexer (5), a buffer memory (13), and the reception circuit memory. In the multiplexer first position an address of the generator is supplied to the memory, while in its second position an address of a read-out address generator (9) is supplied. During the multiplexer change-over time period input data are written and a transparent memory state is generated respectively. ADVANTAGE- Improved buffer memory for phase variations compensation.