| 摘要 |
<p>A circuit for sampling component signals and a regenerating circuit comprising a Δt delaying circuit (5) which delays the phase of a first analog component signal (I1) by a time Δt=(n-1)/(2fs), a first A/D converter (1) which samples the output of the Δt delaying circuit (5) with clocks of a sampling frequency fs and generates a first digital data (O1), a 1/n frequency dividing circuit (4) which divides the clock of the sampling frequency fs and generates a clock of a frequency of fs/n (n is a positive integer other than 1), and a second A/D converter (2) which samples a second analog component signal (I2) being in-phase with the first analog component signals (I1) with the clock of fs/n outputted from the 1/n frequency dividing circuit (4) and generates second digital data (O2).</p> |
