| 摘要 |
PURPOSE:To eliminate the generation of an error at the time of transmitting information and to improve the system reliability by providing a clock phase adjustment circuit which adjusts the phase of the clock signal sent from an external device. CONSTITUTION:A clock phase adjustment circuit 14 is provided together with a central control circuit 16, and an address data pattern generating circuit 18. The circuit 14 adjusts the phase of an internal clock of a device 10 in order to secure the substantial coincidence with the phase of the clock of an external device. Thus the operating synchronization is secured between the device 10 and the external device. As a result, it is possible to cope with an external device which works on an optional clock frequency in a wider range of operating frequencies. Then the generation of errors can be eliminated at the time of transmitting the information and the operating reliability is improved. |
