| 摘要 |
PURPOSE:To realize high speed clock switching such as nearly 8Mb/s from which no device alarm nor data error is caused by providing a circuit system detecting a steady-state phase error of an output clock of an active and a standby PLO circuit so as to control a selection circuit. CONSTITUTION:A changeover control section 3 receiving a PLO alarm signal A' (B') outputted respectively from an active PLO circuit 1 (standby PLO circuit 2) and a manual changeover control signal at a changeover control input terminal 12 generates and outputs a switching control signal C. Moreover, an OR circuit 7 ORs phases of signals E, F taken by an AND circuit 4 catching a leading edge of a slower phase in output clocks A, B of the active PLO circuit 1, the standby PLO circuit 2 and a NOR circuit 5 catching a trailing edge of a slower phase in output clocks A, B of the active PLO circuit 1, the standby PLO circuit 2 and an output G of the OR circuit 7 applies retiming to an output of the changeover control section 3 by using a flip-flop circuit 8. |
