| 摘要 |
PURPOSE:To remove a device with adverse reliability by parallelly providing P channel and N channel transistors at the equalize transistors of both bit lines and applying the inverted signal of a memory cell plate impressing voltage, which is inputted from the outside, as a bit line voltage. CONSTITUTION:First of all, Tr Q3 and Q4 are added as bit line equalize MOS transistors. This is for impressing stress to a bit line BL or for turning to Ov or Vcc. When N channel Tr Q1 and Q2 are turned ON< equalization to the Ov is enabled. When equalizing to the Vcc level, however, the P channel Tr Q3 and Q4 play the role. Thus, on standby for a wafer test, by setting a Vcp5 at Ov or the Vcc, the potential difference of the Vcc is applied between a CP and a BL, and a stress test can be executed. Even in a forwarding test, by providing an introducing means composed of a super Vcc or the like, the stress test similar to the wafer test can be executed, and a memory integrated circuit can be realized with high reliability. |
