发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To prevent a test mode from being erroneously set when a power source is turned on by connecting a power source ON reset means to an external the inverse of RAS input means and connecting the delay means of the power source ON reset means to an external the inverse of WE input means. CONSTITUTION:When the power source is turned on, a power source VCC is fluctuated from an OV level to a VCC level and while receiving this fluctuation, power source ON reset signals POR1 and POR2 are respectively fluctuated form an L level to an H level. Then, an internal the inverse of RAS signal, internal the inverse of CAS signal and the internal the inverse of WE signal are fluctuated to the H level, and reset is started. Continuously, the signal POR1 is fluctuated from the H level to the L level earlier than the POR 2, and the internal the inverse of RAS signal and the internal the inverse of CAS signal are fluctuated to the L level after completing the reset. Further, since the signal POR2 is fluctuated from the H level to the L level, the internal the inverse of WE signal is fluctuated to the L level after completing the reset. Thus, the test mode is not set when completing the reset.
申请公布号 JPH0453089(A) 申请公布日期 1992.02.20
申请号 JP19900160613 申请日期 1990.06.19
申请人 MITSUBISHI ELECTRIC CORP 发明人 FUKIAGE TAKAHIKO
分类号 G11C11/41;G11C11/401;G11C11/405 主分类号 G11C11/41
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