发明名称 |
METHOD AND ARRANGEMENT FOR GENERATING A CORRECTION SIGNAL FOR A DIGITAL TIMING RECOVERY DEVICE |
摘要 |
A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment. |
申请公布号 |
CA1296072(C) |
申请公布日期 |
1992.02.18 |
申请号 |
CA19880583695 |
申请日期 |
1988.11.22 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
SARKOEZI, IMRE |
分类号 |
H04L7/04;H04L7/00;H04L7/02;H04L7/033 |
主分类号 |
H04L7/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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