| 摘要 |
A fine-pitch pin grid array for mounting an IC chip having a number of signal, ground and power contact pads thereon comprises a square as-fired ceramic substrate having a corresponding number of signal, ground and power metal filled vias located on the side portions of the surface thereof. Deposited on the surface of the substrate is a thin-film metallization which includes a corresponding number of signal, ground and power bonding pads located on the sides of the central portion thereof and further includes conductive traces which provide for connecting each signal metal filled via to a signal bonding pad. Deposited over the thin-film metallization is a multilayer circuit which includes a first dielectric layer having a low dielectric constant, a ground metal layer, a second dielectric layer having a high dielectric constant, and a power metal layer. The ground metal layer is used to commonly connect the ground metal filled vias to the ground bonding pads. The power metal layer is used to commonly connect the power metal filled vias to the power bonding pads. The ground and power layers and the intervening second dielectric layer further function as an integrated decoupling capacitor. Moreover, the ground layer further functions to control the impedance of the signal conductive traces.
|
