| 摘要 |
PURPOSE:To perform fast access to a memory cell in a test time even by slow memory large in capacity by using a latch, and supplying each address signal sequentially at every clock pulse. CONSTITUTION:A control circuit supplies the clock pulse to each latch, and also, supplies the address signal sequentially at every clock pulse, and an address latch 23 holds the address signal transiently and supplies it to a row decoder 24, and the decoder 24 decodes a row address, and a row latch 25 holds decoder output transiently, and memory 26 supplies data read out corresponding to the decoder output to a cell latch 27 sequentially, and the latch 27 holds the data transiently, and supplies it to a column decoder 28 sequentially. Furthermore, the decoder 28 decodes a column address corresponding to the address signal, and supplies it to a column latch 29, and the column latch 29 holds the data transiently, and outputs it sequentially. In such a way, a the data in the memory can be read out sequentially at every clock pulse. |
