| 摘要 |
PURPOSE:To realize this circuit through the employment of two data latch circuits only corresponding to a digital signal source by providing a logic circuit delaying an input digital signal by a predetermined time so as to output a detection signal representing a level change in the digital signal on the detection circuit. CONSTITUTION:When the level of a digital signal source 1 falls down, the output level of an inverter 11 rises, a data latch circuit (DL) 3 latches the high level of its D input and its output Q goes to a high level. With the output Q of the DL 3 set to a high level, the output of an OR circuit (OR) 7 goes to a high level and the output Q of a DL 8 goes to a high level synchronously with the rise of a detection clock signal. Similarly, when the digital signal source 1 rises, a DL 4 latches a high level, when a digital signal source 2 falls down, a DL 5 latches a high level, and when the digital signal source 2 rises,a DL 6 latches a high level and the processing is implemented similarly with the above-mentioned operation. |
