| 摘要 |
PURPOSE:To realize a channel of an optional band width as required by delaying 0th to (N-1)th filtered signals by delay of 0-(N-1) samples respectively, adding the results, converting the sum into a serial signal and outputting the serial signal as a signal subject to FDM multiplexing. CONSTITUTION:The circuit is provided with 1st-(N-l)th frequency conversion circuits 4-1-4-(N-1) and a k-th frequency conversion circuit 4-k applies frequency conversion of 0(Hz) fk=k.DELTAf(Hz). The center frequency of an input signal is frequency-converted from 0(Hz) to fk(Hz). Then the signal is given to filters 2-0-2-(N-1) tuned to a same frequency fk. Thus, a filter bank having a completely flat frequency characteristic in a band of each channel is realized. |
