| 摘要 |
A disc drive controller has read post compensation which corrects for peak shift effects on discs with insufficient precompensation. The data is recorded in Manchester (MFM) format and read into circuitry including SCT counter (451) which loads parameters representing a cell with a short-cell (2 unit) following it and LCT counter (453) which loads parameters representing a cell with a long cell (3 or 4 unit) following it. Bound detector 455 counts the number of pulses between transitions and shift registers (457, 459) store the number of pulses generated by the respective counters to enable the bound detector to generate peak shift compensated pulses. The controller has a programmable parameter scheme which makes it possible to read and write 3 1/2 inch variable and fixed speed drives, as well as standard 5 1/4 inch drives. Additionally, there is a plus/minus rate multiplier to correct for symmetry and frequency errors. The use of half clock circuits to provide half clock resolution in the signal being written to and read from the disk is provided with the capability of operating at continuously variable clock speeds and data rates dynamically programmable by the computer. <IMAGE> |
