| 摘要 |
PURPOSE:To prevent parasitic effect of a minute CMOS device by a method wherein an FET is formed on the substrate and the well region, while a doped poly- silicon wiring is provided in the well boundary part to form a high concentration region of the same conductivity type on the well. CONSTITUTION:For instance, the P-type substrate 22 is provided with an N-well 23 of phosphor concentration 8X10<15>/cm<2>, a minute FET is formed on the substrate 22 and the well 23 to be made into a CMOS1. Each FET is of Si gate type, while the inverse conductivity type source-drain regions are formed to be shallow about 0.5mum by ion injection. The boundary part between the well 23 and the substrate 22 is provided with a high concentration phosphor-droped polysilicon wiring 31 and having this as the diffusion source an N<+> region 30 of abut 1mum depth is formed. Also the substrate 22 is provided with a P-region 35 for preventing inversion. Thereby the layer resistance of the well 23 can be made low, and the potential inside of the well can be fixed thus making the latchup phenomenon hard to arise so as to make the device highly reliable. |
