| 摘要 |
<p>A multiprocessor system includes at least one copy-back cache memory (M1) connected via a system bus to a common memory (CM). The copy-back cache memory includes a specific flag (S) for indicating whether an identical data is shared with other cache memories, a first unit (P1) for intercepting a response of the common memory to an access when it detects the access from another cache memory to a region where the specific flag is OFF, a second unit (P2) for transferring to the other cache memory an entry corresponding to a region indicated by the access address from the other cache memory and turning ON the specific flag, and a third unit (P3) for sending out a write address to the system bus and turning OFF the specific flag where a write into a shared and modified entry is carried out, to thereby invalidate a corresponding entry in the other cache memory based on the write address. As a result, it is possible to reflect an updated data on another cache memory even if data is newly written into a corresponding entry in the self cache memory after the transfer of the entry to another cache memory, and thus contributes to an improvement in the performance of the entire system.</p> |
