| 摘要 |
A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (Vp), but preferably close to Vp so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias current. The input JFETs are cascoded with another pair of JFETs, and the gate-source circuits for the JFETs of each branch are connected in series with the gate-source circuit of an additional JFET between the gates and drains of the input JFETs. The additional JFET is supplied with a current that is substantially less than IDSS, and thus develops a significant portion of the necessary gate-drain voltages for the input JFETs. This enables a significant net reduction in the chip surface area occupied by the stage.
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