发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To obtain a synchronizing signal having extremely high phase accuracy to an external signal regardless of the simple configuration by executing phase correction to the output of a synchronizing signal selection circuit. CONSTITUTION:This phase locked loop is equipped with a synchronizing signal selecting means 5, signal arrival detecting means 60, second delay means 70, delay position discriminating means 600, delay position deciding means 65, internal delay means 720, third delay means 700, delay time selecting means 750, stop signal preparing means 760, source signal selecting means 770 and logic synthesizing means 780. Then, the output signal of the synchronizing signal selection circuit 5 is outputted after correcting the phase based on a trigger signal. Thus, the phase synchronizing circuit to realize the phase and frequency accuracy by using general-purpose active elements can be realized with the simple configuration at low cost.
申请公布号 JPH0440016(A) 申请公布日期 1992.02.10
申请号 JP19900146878 申请日期 1990.06.04
申请人 YOKOMIZO AKIRA 发明人 YOKOMIZO AKIRA
分类号 H03L7/00 主分类号 H03L7/00
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