| 摘要 |
PURPOSE:To realize the high speed memory read operation executed by a high speed operation frequency by sending out data read out of a memory to a processor, and simultaneously, executing the detection of a 1-bit error by this data and a parity bit. CONSTITUTION:The device is provided with a data memory 2, a check bit/parity bit memory 11 in which a check bit and a parity bit for detecting and correcting an error are stored, a syndrome generator 4b, a 2-bit error detector 10b for detecting the generation of a 2-bit error from a syndrome pattern, and a 1-bit error detector 10c for detecting the generation of a 1-bit error, based on the data and the party bit. In such a state, when generation of a 1-bit error is detected, a processor 1 is allowed to execute memory read and it is corrected by an error correcting device 4f. In such a way, by shortening the time for deciding a result of detection, a read cycle by a high speed operation frequency can be realized. |
