发明名称 TIMING CIRCUIT
摘要 <p>PURPOSE:To shorten the sampling time when the input data are latched by supplying a clock different from that supplied to an internal circuit to an input terminal which fetches the external information so as to secure the input timing. CONSTITUTION:The clock CLK impressed to an external clock input terminal 1 produces an internal clock 4 through an input buffer 2 and a clock generating circuit 3. Then a clock different from the clock 4 supplied to an internal circuit is supplied to an input terminal 5 which fetches the external information so that the input timing is secured. That is, the data on the terminal 5 are latched by an input latch circuit 7 with use of the output of the buffer 2. In this case, both maximum and minimum widths are reduced. Thus the sampling time of the input data is shortened.</p>
申请公布号 JPH0437942(A) 申请公布日期 1992.02.07
申请号 JP19900145116 申请日期 1990.06.01
申请人 MITSUBISHI ELECTRIC CORP 发明人 HATA MASAYUKI
分类号 G06F13/42;G06F1/12 主分类号 G06F13/42
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