发明名称 ASYNCHRONOUS DATA TRANSMISSION METHOD
摘要 <p>PURPOSE:To eliminate the deviation of the phase of clock between a sender side MODEM and a sender side TDM (multiplexer) by resetting a data buffer when the start of an asynchronous data is detected. CONSTITUTION:An FIFO control circuit 8 sends an FIFO output clock 11 to an FIFO buffer 9 in matching with a high speed clock 6 after data of a prescribed number relating to a preceding burst number are stored in the FIFO buffer 9 so that the data in the FIFO buffer 9 are not lost from the start of transmission of a facsimile data till its end. A dummy data is sent for a while after the end of the facsimile data, but since the FIFO buffer 9 is again reset at the start of the facsimile data, the dummy data in the FIFO buffer 9 is lost. The loss of the dummy data is allowed and the synchronization is taken at the start of the succeeding facsimile data regardless of lead or lag and the phase deviation is avoided.</p>
申请公布号 JPH0437333(A) 申请公布日期 1992.02.07
申请号 JP19900143392 申请日期 1990.06.01
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAMADA YOSHIKO
分类号 H04J3/00;H04J3/02;H04L7/00 主分类号 H04J3/00
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