发明名称 MEMORY ERROR CHECK AND CONTROL SYSTEM
摘要 PURPOSE:To shorten a time required for generating a nullifying signal, by nullifying an output of a microinstruction based on an output of an error detection signal input means for displaying a 1 bit error or a 2 bit error, when it has occurred. CONSTITUTION:A mu-instruction is read out together with a check bit from a memory for a micro mu program PG, and is checked, and as a result, when one of syndrome SD constitution bits S0-S5 becomes ''1'', a nullifying signal INVLD is supplied to a mu-instruction decoded destination through an OR circuit 1. In case when an error is 1 bit error, after the nullifying signal has been generated, the SD constitution bit S6 becomes ''1'', and a correct timing signal CSCRT for correcting the mu-instruction is generated from an FF5 through an AND circuit 3. When the bit S6 becomes ''1'', a signal CSSGL for informing the existence of the 1 bit error is generated to an output of the memory for the muPG from an FF6. In case when an output of the circuit 1 is ''1'' and the bit S6 is ''0'', a signal CSDBLE for informing the existence of the 2 bit error is generated to an output of the memory for the muPG from an FF7 through an AND circuit 4.
申请公布号 JPS5725048(A) 申请公布日期 1982.02.09
申请号 JP19800100956 申请日期 1980.07.23
申请人 FUJITSU LTD 发明人 SAKAI KENJI;AOKI TAKASHI
分类号 G06F11/10;G06F12/16;H03M13/00 主分类号 G06F11/10
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