The precharge and equalisation circuit has a precharge N-channel MOS transistor having its drain connected to a supply potential and its source connected to a bit line. A second precharge N-channel MOS transistor has its drain connected to the supply potential and its source connected to a second bit line. The first and second precharge transistors have their gates connected together and to a first input node for receiving a true precharge signal. An equalisation P-channel MOS transistor has its source connected to the first bit line and its drain connected to a common node which is coupled to a current-sinking circuit positioned external to the memory array for sinking current. A second equalisation P-channel MOS transistor has its source connected to the second bit line and its drain connected to the common node. The equalisation transistors have their gates connected together and to a second input node for receiving a complementary equalisation signal.
申请公布号
DE4117684(A1)
申请公布日期
1992.02.06
申请号
DE19914117684
申请日期
1991.05.29
申请人
ANDRITZ-PATENTVERWALTUNGS-GESELLSCHAFT MBH, GRAZ, AT
发明人
PINKAS, WOLFGANG, DIPL.-ING. DR.TECHN., MITTERLASSNITZ, AT;SCHROETTNER, ERWIN, ING., ATTENDORFBERG, AT