Multichannel read-write memory for information processor - has decoder for decoding selected addresses for interrupt via several channels

摘要

The multiple channel read/write memory connected to a central unit contains an interrupt circuit stage, a memory section and a number of data communications channels, each corresp. to an external device. The interrupt stage contains a decoder section for decoding a number of defined addresses for performing interrupts via the channels, and a selection circuit for the selection from the addresses. USE - In information processor of flexible processing power to enable complex processing to occur during multiple address interrupt handling.