| 摘要 |
<p>The I/O control circuit is used regardless of the type of central processing units (CPU) of facsimile. The circuit includes a first decoder (10) for decoding input addresses (A4-A6) according to chip select signal and I/O R/W enable signal, a second decoder (20) for decoding input addresses (A1-A3) according to chip select signal, an address latch (200) for generating decoding output (On1-On8) according to one output signal of the first decoder (10) , a multiplexer (300) enabled by one output signal of the first decoder (10) for selecting one signal of multiplexing input and for transmitting to an I/O data bus according to the state of input selection signal, a first demultiplexer (DEMUX1) for generating decoding output (Q0-Q7) according to the state of output selection signal, and a second multiplexer (MUX2) for generating a first clock signal.</p> |
