发明名称 DIGITAL SIGNAL PROCESSING PROCESSOR
摘要 <p>PURPOSE:To improve the processing capability of a processor and to reduce the circuit forming area by not only outputting a provate address to a storage part but also stopping address update of a program memory at the time of storing transmission data or reception data having preliminarily set data length in the storage part. CONSTITUTION:When transmission data or reception data whose data length is set to a data length setting register 311 is stored in a storage part 321. The private address outputted from a private address generating part 322 is outputted to the storage part 321, and address update of a program memory 313 is stopped by an address change stop means 312a, and transmission or reception data in the storage part 321 is transferred. Consequently, a buffer memory for storage of serial packet data and its control circuit are unnecessary, and data is directly transmitted and received. Thus, the circuit forming area is reduced and the processing capability is improved.</p>
申请公布号 JPH0435541(A) 申请公布日期 1992.02.06
申请号 JP19900142668 申请日期 1990.05.31
申请人 OKI ELECTRIC IND CO LTD 发明人 KIHARA KOICHI;KOBAYASHI HIROKI
分类号 G06F13/12;H04L12/951 主分类号 G06F13/12
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