| 摘要 |
<p>A multiple interrupt handling circuit comprising a mask register (4) for latching desired information from a microprocessor to generate a mask signal; a latch register (5) for latching desired information from said microprocessor to generate a latch signal; a plurality of interrupt units (6), each for inputting said mask signal and said latch signal from said mask and latch register (4,5) and a corresponding interrupt input signal and generating in sequence a corresponding interrupt output signal in response to a clocking signal based on a system interrupt signal; an encoder (7) for encoding said interrupt output signals from said plurality of interrupt units (6) to generate a plurality of status signals; and a control unit (9) for combining desired information signals from said microprocessor in read and write of information. Therefore, in accordance with the present invention, a multiplicity of interrupts can be handled all without exception in a system utilizing the microcomputer. More particularly, the present multiple interrupt handling circuit can be IC-ed such that it can be used as an interrupt handling-dedicated IC and contained in the central processing unit, thereby allowing its simple construction. <IMAGE></p> |
