| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a frequency dividing circuit which is reduced in number of components, improved in layout efficiency, and can generate frequency dividing signals of about 50% in duty ratio. SOLUTION: A frequency dividing circuit gives the logically-operated signal of the output signals of a K.T delay circuit 80a which delays K-cycle input signals IN and feedback signals through the feedback section 80d of an M.T delay circuit 80c which delays M-cycle input signals to the M.T delay circuit 80c. The frequency dividing circuit adjusts the duty ratio of the signals which are shifted in phase by K/2 cycle from the input signals of the signals generated from the M.T delay circuit 80c by ANDing/ORing the signals by means of a duty adjusting circuit 80e.</p> |
