Data amplifying system in semiconductor memory device.

摘要

A data amplifying system in a semiconductor memory includes a current mirror circuit (2) for receiving, via a data bus (DB, DB), an input signal (In, IN) corresponding to data read out from a memory cell (1a, 1b) via a pair of bit lines (BL, BL) and for amplifying the input signal. The current mirror circuit operates on the basis of a power supply voltage (Vcc). An amplitude limit circuit (3) receives an operation voltage (Vcc/2) and limits the amplitude of the input signal on the data bus to a predetermined potential range on the basis of the operation voltage. A bit line reset potential generator (5) generates a bit line reset potential (Vcc/2) and applies the bit line reset potential to the bit lines and the amplitude limit circuit. The bit line reset voltage is lower than the power supply line and serves as the operation voltage applied to the amplitude limit circuit. <IMAGE>