| 摘要 |
<p>A frequency divider comprising an input port (4), for receiving an input signal, a counting means (42, 52)and a retiming means (30), the input port (4) being coupled to an input of the retiming means (30), the counting means (42, 52) including first flip-flop means (42) having its clock input coupled to said input port (4), and second flip-flop means (52) having its clock input coupled to an output of said first flip-flop means (42) and an output coupled together with an output of the first flip-flop means (42) via gate means (54) to a control input of the retimer means (30), said counting means (42, 52) selectively enabling the retiming means (30) so that the retiming means (30) changes state on receipt of a cycle of the input signal following enablement whereby the output of the retiming means (30) provides a frequency divided version of the input signal which is synchronised with the input signal. <IMAGE></p> |
